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Publications

Conference/Symposium Papers:

  • H. Sabaghian, P. Behnam, B. Alizadeh, and Z. Navabi, Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach, ISVLSI 2017, Germany (to appear).
  • S. Salamat, M. Ahmadi, B. Alizadeh, and M. Fujita, Systematic Approximate Logic Optimization Using Don’t Care Conditions, ISQED 2017, USA, pages 419-425.
  • S. BeigMohammadi, and B. Alizadeh, Combinational Trace Signal Selection with Improved State Restoration for Post-silicon Debug, DATE 2016, Germany, pages 1369-1374.
  • P. Behnam, B. Alizadeh, S. Taheri, and M. Fujita, Formally Analysing Fault Tolerance in Datapath Designs using Equivalence Checking, ASPDAC 2016, Macao, pages 133-138.
  • P. Behnam, and B. Alizadeh, In-circuit Mutation-based Automatic Correction of Certain Design Errors using SAT Mechanisms, ATS 2015, India, pages 199-204.
  • A. Mahzoon, and B. Alizadeh, Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization, ISVLSI 2015, France, pages 243-248.
  • M. Ahmady, B. Alizadeh, and B. Forouzandeh, A Timing Error Mitigation Technique for High Performance Designs, ISVLSI 2015, France, pages 428-433.
  • A. Mahzoon, B. Alizadeh, and M. Fujita, HOFEX: High Level Optimization of Floating Point Expressions for Implementation on FPGAs, IWLS 2015, USA.
  • S. R. Sharafinejad, B. Alizadeh, and M. Fujita, UPF-based Formal Verification of Low Power Techniques in Modern Processors, VTS 2015, USA, pages 1-6.
  • F. Refan, B. Alizadeh, and Z. Navabi, Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging, VTS 2015, USA, pages 1-6.
  • S. Ghandali, B. Alizadeh, and Z. Navabi, Low Power Scheduling in High Level Synthesis using Dual-Vth Library, ISQED 2015, USA, pages 507-511.
  • E. Qasemi, M. H. Shadmehr, B. Azizian, A. Samadi, S. Mozaffari, A. Shirian, and B. Alizadeh, Highly Scalable, Shared Memory, Monte-Carlo Tree Search based Blokus Duo Solver on FPGA, ICFPT 2014, China, pages 370-373.
  • H. Mehri, and B. Alizadeh, An Analytical Dynamic and Leakage Power Model for FPGAs, ICEE 2014, Iran, pages 300-305.
  • H. Haghbayan, B. Alizadeh, A. Rahmani, P. Liljeberg and H. Tenhunen, Automated Formal Approach for Debugging Dividers Using Dynamic Specification, DFT 2014, Netherlands, pages 264-269.
  • F. Farahmandi, B. Alizadeh, and Z. Navabi, Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits, ISVLSI 2014, USA, pages 338-343.
  • V. Janfaza, P. Behnam, B. Forouzandeh, and B. Alizadeh, A Low-power Enhanced Bitmask-dictionary Scheme for Test Data Compression, ISVLSI 2014, USA, pages 220-225.
  • S. Sadeghi-kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, Improving Polynomial Datapath Debugging with HEDs, ETS 2014, Germany, pages 1-4.
  • P. Behnam, B. Alizadeh, and Z. Navabi, Automatic Correction of Certain Design Errors using Mutation Technique, ETS 2014, Germany, pages 1-2.
  • M. Nejat, B. Alizadeh, and A. Afzalikusha, Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits, DATE 2014, Germany, pages 1-4.
  • S. Ghandali, B. Alizadeh, M. Fujita, and Z. Navabi, RTL Datapath Optimization using System-level Transformations, ISQED 2014, USA, pages 309-316.
  • M. H. Haghbayan, B. Alizadeh, P. Behnam, and S. Safari, Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism, VLSI Design 2014, India, pages 80-85.
  • P. Behnam, H. Sabaghian, B. Alizadeh, K. Mohajerani, and Z. Navabi, A Probabilistic Approach for Counterexample Generation to Aid Design Debuging, EWDTS 2013, Russia, pages 1-5.
  • B. Alizadeh, and M. Fujita, A Functional Test Generation Technique for RTL Datapaths, HLDVT 2012, USA, pages 64-70.
  • P. Behnam, B. Alizadeh, Z. Navabi, and M. Fujita, Mutation-based Debugging Technique with Auto-correction Mechansim for RTL Designs, SDD 2012, USA.
  • S. Ghandali, B. Alizadeh, Z. Navabi, and M. Fujita, Polynomial Datapath Synthesis and Optimization Based on Vanishing Polynomial over Z2m and Algebraic Techniques, MEMOCODE 2012, USA, pages 65-74.
  • B. Alizadeh, A Formal Approach to Debug Polynomial Datapath Designs, ASP-DAC 2012, Australia, pages 683-688.
  • B. Alizadeh, A Symbolic Model-based Diagnosis With Auto-correction Framework for Arithmetic Circuits, ASQED 2011, Malaysia, pages 195-202.
  • B. Alizadeh, and M. Fujita, Early Case-splitting and False Path Detection to Improve High Level ATPG Techniques, ISCAS 2011, Brazil, pages 1463-1466.
  • B. Alizadeh, and M. Fujita, Debugging and Optimizing High Performance Superscalar Out-of-Order Processors Using Formal Verification Techniques, ISQED 2011, USA, pages 1-6.
  • B. Alizadeh, and M. Fujita, A Debugging Method for Repairing Post-Silicon Bugs of High Performance Processors in the Fields, ICFPT 2010, China, pages 328-331.
  • M. Fujita, B. Alizadeh, H. Yoshida and T. Matsumoto, Post-silicon Debugging with High Level Design Descriptions and Programmable Controllers, MTV 2010, USA, pages 11-15.
  • F. Haedicke, B. Alizadeh, G. Fey, M. Fujita, R. Drechsler, Polynomial datapath optimization using constraint solving and formal modeling, ICCAD 2010, USA, pages 756-761.
  • B. Alizadeh, A.M. Gharehbaghi and M. Fujita, Pipelined Microprocessors Optimization and Debugging, ARC 2010, Thailand, pages 435-444.
  • A.M. Gharehbaghi, B. Alizadeh and M. Fujita, Aggressive Over-clocking Support using a Novel Timing Error Recovery Technique on FPGAs, Symposium on FPGA 2010, USA.
  • B. Alizadeh and M. Fujita, Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach, ASP-DAC 2010, Taiwan, pages 425-430.
  • B. Alizadeh and M. Fujita, Improved Heuristics for Finite Word-Length Polynomial Data-path Optimization, ICCAD 2009, USA, pages 169-174.
  • B. Alizadeh and M. Fujita, Modular Arithmetic Decision Procedure with Auto-correction Mechanism, HLDVT 2009, USA, pages 138-145.
  • B. Alizadeh and M. Fujita, Optimization of Modular Multiplication on FPGA using Don’t Care Conditions, ICFPT 2009, Australia, pages 399-402.
  • B. Alizadeh and M. Fujita, Modularity in Word-level Decision Diagrams, RM 2009, Japan, pages 33-41.
  • O. Sarbishei, B. Alizadeh and M. Fujita, Polynomial Data-path Optimization using Partitioning and Compensation Heuristics, DAC 2009, USA, pages 931-936.
  • O. Sarbishei, B. Alizadeh and M. Fujita, A Debug Methodology for Arithmetic Circuits based on Horner Decision Diagrams, CFV 2009, France, pages 30-45.
  • O. Sarbishei, M. Tabandeh, B. Alizadeh and M. Fujita, High-level Optimization of Integer Multipliers over a Finite Bit-width with Verification Capabilities, MEMOCODE 2009, USA, pages 56-65.
  • B. Alizadeh and M. Fujita, Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions, CFV 2008, Australia, pages 22-40.
  • O. Sarbishei, B. Alizadeh and M. Fujita, Arithmetic Circuits Verification without Looking for Internal Equivalences, MEMOCODE 2008, USA, pages 7-16.
  • B. Alizadeh and M. Fujita, Sequential Equivalence Checking using a Hybrid Boolean-Word Level Decision Diagram, CSICC 2008, Iran.
  • M. Momtazpour, M. Tabandeh and B. Alizadeh, System-level Implementation of DSP Applications on FPGA, CSICC 2008, Iran.
  • B. Alizadeh and M. Fujita, A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers, HLDVT 2007, USA, pages 97-104.
  • B. Alizadeh and M. Fujita, A Hybrid Approach for Equivalence Checking between System Level and RTL Descriptions, IWLS 2007, USA, pages 298-304.
  • B. Alizadeh and M. Fujita, LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware/Software Co-designs, CFV 2007, Germany, pages 15-29.
  • M. R. Saadat, M. Momtazpour and B. Alizadeh, Simulation and Improvement of Two Digital Adaptive Frequency Calibration Techniques for Fast Locking Wide-Band Frequency Synthesizers, DTIS 2007, pages 136-141.
  • B. Alizadeh and M. Fujita, Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions, Automated Technology for Validation and Analysis, Lecture Notes in Computer Science, Vol. 4762, November 2007, pages 129-144.
  • B. Alizadeh, Word Level Functional Coverage Computation, ASP-DAC 2006, Japan, pages 7-12.
  • A. Hooshmand, S. Shamshiri, M. Alisafaee, B. Alizadeh, P. Lotfikamran, M. Naderi and Z. Navabi, Binary Taylor Diagrams: An Efficient Implementation of Taylor Expansion Diagrams, ISCAS 2005, Japan, pages 424-427.
  • B. Alizadeh and Z. Navabi, Using Integer Equations to Check PSL Properties in RT Level Design, IWSOC 2004, Canada, pages 83-86.
  • B. Alizadeh and Z. Navabi, Symbolic Simulation Based on Integer Equations in Processor Verification, EDP 2004, USA, pages 202-209.
  • B. Alizadeh and Z. Navabi, Property Checking Based on Hierarchical Integer Equations, ACSD 2004, Canada, pages 26-35.
  • B. Alizadeh and M.R. Kakoee, Using Integer Equations for High Level Formal Verification Property Checking, ISQED 2003, USA, pages 69-74.
  • B. Alizadeh, H.R. Hashempour and Z. Navabi, A VHDL Based Integrated Environment for Reliable System Design, NATW 1998, USA.
  • B. Alizadeh, S.M. Fakhraei and Z. Navabi, Switch Level Simulation in VHDL, Computer Society Conference 1998, IRAN.
  • B. Alizadeh and Z. Navabi, Component Modeling for Reliability by simulation, VIUF 1997, USA.