فارسی | En

From simple home appliances to space shuttles, embedded systems are widely used. With the ever increasing complexity of embedded systems, design, verification and debug of such systems is becoming more and more challenging. Design of a complex embedded system requires engineering teams, precise plans and schedules, heavy computer simulations, and verification both before and after fabrication. At Design, Verification and Debug of Embedded Systems (DVDES) Lab., we’re continuously looking for ways to facilitate the embedded system design flow through development of new tools and methods for fast realization of reliable high-performance embedded systems. With today’s complex systems, 70% of total design time consists of their verification and debug. DVDES Lab. aims to cut off this share by incorporating dynamic, assertion-based and formal verification steps in its tools and methods.


PhD Students

Seyed Reza Sharafinejad

PhD Candidate

Email: r.sharafi@ut.ac.ir

The power consumption is one of the important considerations and constraints in the modern processor’s design, so that portable devices must have limited power budget to extend battery life, reduce noise and heat impacts and increase reliability. In order to meet the stringent power budgets of low-power digital designs, several power management techniques such as clock gating, power gating and dynamic voltage frequency scaling (DVFS) have been used in industrial practice. As a result, adding the power management techniques to a design has caused new bugs in the verification task in addition to traditional functional bugs. Also, whatever these techniques become more complex, the verification of these designs is faced more serious challenges. The focus of this thesis project is on two goals, simultaneously: 1) ensuring the correctness of the design after insertion of power management parts so that functionality of the design doesn’t change. The golden reference for this goal is a specification model without power features while the implementation model is a low-power pipelined processor with several power management strategies. 2) Checking the accuracy applying of high-level power strategies to the low-level power control circuitry defined in the UPF.

Siamack BeigMohammadi

PhD Candidate

Email: siamackbm@yahoo.com

Pre-silicon verification methods provide full coverage over circuit states which accelerates further bug localization and debugging processes. However, with ever increasing design complexity and reduced time-to-market some bugs escape to silicon. Thus, post-silicon verification and debug which runs orders of magnitude faster- is becoming crucial. The main challenge with post-silicon debug is limited observability of internal circuit nodes to which several solutions have been proposed. The goal of my thesis is to facilitate post-silicon verification and debug through development of new tools and techniques.

Masoud shiroei

PhD Candidate

Email: shiroei@ut.ac.ir

VLSI circuit design and synthesis processes are error prone. Consequently, verification, bug localization and correction methodologies in different level of abstraction are developed by researches. Even in well designed circuits, modification due to Engineering Change Order (ECO) is probable. The complete VLSI circuit design process from high-level specification to layout is a time consuming and costly process. Consequently, partial synthesis methodologies in different abstraction level are developed to modify designs in lower cost and less time. Short time to market and ever-growing design complexity made industry to develop and apply high-level synthesis methodologies. My thesis is about developing a partial high-level synthesis methodology. Currently, I am developing an ECO mitigating technique for designs at Register Transfer Level (RTL) based on partial high-level synthesis.

Ali Azarmi

PhD Student

Email: aliazarmi@ut.ac.ir

In recent years, deep artificial neural networks (including recurrent ones) have won numerous contests in pattern recognition and machine learning. Learn about artificial neural networks and how they're being used for machine learning, as applied to speech and object recognition, image segmentation, modeling language and human motion, etc. The goal of my thesis is working with deep supervised learning, unsupervised learning, reinforcement learning and evolutionary computation to implement an useful and brain-based product in this area.

pouria mirebrahimi

PhD Student

Email: pouria.mirebrahimi@gmail.com

Interest in Brain-Computer Interfacing (BCI) is growing. This can be concluded from its forward-looking applications, environment, and devices that can range from wheelchairs and artificially controlled hands for grasping, to entertainment applications including artful visualization, digital painting, game control, interaction with social robots or virtual humans, and domestic applications. The growing trend is for researchers and experts in this area to move on the next-generation of Neural Signal Processors (NSP) for BCIs which ease the data bandwidth, processing capability, and power consumption constriction, for implantable cases especially. In my thesis, a hardware-efficient and low-power neural decoder for dense electrode arrays will be proposed.

MSc Students

Mojtaba Abbasnezhad

MSc Student

Email: mojtaba.abasnezhad@gmail.com

Distributed fiber optic sensing offers the ability to measure temperatures and strains at thousands of points along a single fiber. This is particularly interesting for the monitoring of large structures such as dams, dikes, levees, tunnels, pipelines and landslides, where it allows the detection and localization of movements and seepage zones with sensitivity and localization accuracy unattainable using conventional measurement techniques. The main challenges with Distributed fiber optic Sensors are the SNR of the backscatter signal and the Spatial Resolution of the system. The goal of my thesis is to improve these two parameters by signal processing techniques.

Mohammad Emad

MSc Student

Email: miremaad2@gmail.com

In recent years, Convolutional Neural Network (CNN) based methods have achieved great success in a large number of applications and have been among the most powerful and widely used techniques in computer vision. However, CNN-based methods are computational-intensive and resource-consuming, and thus are hard to be integrated into embedded systems such as smart phones, smart glasses, and robots. FPGA is one of the most promising platforms for accelerating CNN, but the limited bandwidth and on-chip memory size limit the performance of FPGA accelerator for CNN. The goal of this thesis is introducing a new hardware accelerator for CNN that achieves close to 100% computational efficiency and is efficient in power and resource usage.

Mohammad sabri

MSc Student

Email: msabri1372@gmail.com

Hardware Trojan attacks have emerged as a major security concern for integrated circuits (ICs) . These attacks relate to malicious modifications of an IC during design or fabrication in an untrusted design house or foundry, which involve untrusted people, design tools, or components. Such modifications can give rise to undesired functional behavior of an IC, or provide covert channels or backdoor through which sensitive information can be leaked.

BSc Students

Former Students

PhD Students

Fatemeh Refan

Mahdieh Grailoo

Mehrnaz Ahmadi

MohamadReza Azarbad

MSc Students

Farimah Farahmandi

Peyman Behnam

Hossein Mehri

Bahman Ajami

Mehrzad Nejat

Alireza Mahzoon

Arash Golgol

Alireza Nahvi

Ali Jahanshahi

Shayan Moini

Mahdi Shakeri

Vahid Saadatmand

BSc Students

Nazanin Farahpour

Sina Shah Hosseini

Seyed Sina Dezfouli

Amir Hossein Borghei

Ehsan Ghasemi

Mohammad Hossein Ghasemi

Amir Samadi

Niloofar Parsajam

Sahand Salamat

Maryam Sadeghi

About LAB

This LAB is mainly focusing on:

  • Digital System Verification and Debug
  • Design Automation of Embedded Systems
  • Reconfigurable Computing
  • Hardware Security
  • Post-silicon Debug
  • Neural Networks