فارسی | En

From simple home appliances to space shuttles, embedded systems are widely used. With the ever increasing complexity of embedded systems, design, verification and debug of such systems is becoming more and more challenging. Design of a complex embedded system requires engineering teams, precise plans and schedules, heavy computer simulations, and verification both before and after fabrication. At Design, Verification and Debug of Embedded Systems (DVDES) Lab., we’re continuously looking for ways to facilitate the embedded system design flow through development of new tools and methods for fast realization of reliable high-performance embedded systems. With today’s complex systems, 70% of total design time consists of their verification and debug. DVDES Lab. aims to cut off this share by incorporating dynamic, assertion-based and formal verification steps in its tools and methods.



Students


PhD Students


MohamadReza Azarbad

PhD Candidate

Email: mohammadreza.azarbad@gmail.com

The ever growing complexity of digital system designs and the critical role of products time-to-market increase the demand for high level synthesis (HLS). Existence of various transformations in HLS makes it an error-prone process in which any bug will propagate to lower abstraction levels and can lead to enormous damages. So, equivalence checking between the high level description and the generated RTL is of great matter of concern. In my dissertation, new formal methods are proposed to verify the equivalence of a given high level description and its implementation considering the scalability issue as well as the false negative problem in this context.


Fatemeh Refan

PhD Candidate

Email: fatemeh_refan@ut.ac.ir

The new requirements in digital system field have led to the increasing complexity of designs. This, in addition to the low scalability of verification methods, and the pressure to shorten time to market causes the incomplete pre-silicon verification and consequently escape of hidden bugs to the post-silicon phase. The restricted controllability and observability of debugging at post-silicon, the lengthy error traces at this phase, and the very special situation in which errors arise on the other hand, turn the post-silicon debugging a necessary and in the same time a challenging problem. Although many works have targeted the automation and effective debugging at pre-silicon phase, the proposed methods are not reusable at post-silicon phase. The goal of this dissertation is to fill this gap by utilizing methods and results obtained from pre-silicon debugging in the post-silicon phase effectively. This can be done in four steps by applying different design bugs including real, statistical, and random bugs, application of automatic verification and debugging on test cases in pre-silicon affected by these bugs to have counterexamples (CEX), and finally establishing an effective connection between debugging at pre and post-silicon phase to enhance and lower the costs of post-silicon debugging and repair.


Seyed Reza Sharafinejad

PhD Candidate

Email: r.sharafi@ut.ac.ir

The power consumption is one of the important considerations and constraints in the modern processor’s design, so that portable devices must have limited power budget to extend battery life, reduce noise and heat impacts and increase reliability. In order to meet the stringent power budgets of low-power digital designs, several power management techniques such as clock gating, power gating and dynamic voltage frequency scaling (DVFS) have been used in industrial practice. As a result, adding the power management techniques to a design has caused new bugs in the verification task in addition to traditional functional bugs. Also, whatever these techniques become more complex, the verification of these designs is faced more serious challenges. The focus of this thesis project is on two goals, simultaneously: 1) ensuring the correctness of the design after insertion of power management parts so that functionality of the design doesn’t change. The golden reference for this goal is a specification model without power features while the implementation model is a low-power pipelined processor with several power management strategies. 2) Checking the accuracy applying of high-level power strategies to the low-level power control circuitry defined in the UPF.


Siamack BeigMohammadi

PhD Student

Email: siamackbm@yahoo.com

Pre-silicon verification methods provide full coverage over circuit states which accelerates further bug localization and debugging processes. However, with ever increasing design complexity and reduced time-to-market some bugs escape to silicon. Thus, post-silicon verification and debug which runs orders of magnitude faster- is becoming crucial. The main challenge with post-silicon debug is limited observability of internal circuit nodes to which several solutions have been proposed. The goal of my thesis is to facilitate post-silicon verification and debug through development of new tools and techniques.


Masoud shiroei

PhD Student

Email: shiroei@ut.ac.ir

VLSI circuit design and synthesis processes are error prone. Consequently, verification, bug localization and correction methodologies in different level of abstraction are developed by researches. Even in well designed circuits, modification due to Engineering Change Order (ECO) is probable. The complete VLSI circuit design process from high-level specification to layout is a time consuming and costly process. Consequently, partial synthesis methodologies in different abstraction level are developed to modify designs in lower cost and less time. Short time to market and ever-growing design complexity made industry to develop and apply high-level synthesis methodologies. My thesis is about developing a partial high-level synthesis methodology. Currently, I am developing an ECO mitigating technique for designs at Register Transfer Level (RTL) based on partial high-level synthesis.


Mehrnaz Ahmadi

PhD Candidate

Email: m.ahmady@ut.ac.ir

The demand for high performance designs which are not susceptible to variations has been significantly increasing over the past few years. Traditionally, in worst case design methodology the maximum allowable frequency (MAF), in which a circuit works correctly, is computed based on the delay of the longest paths (critical paths) in the circuit. My thesis is intended to investigate new techniques to improve the performance of digital circuits beyond the limit of MAF of designs. these techniques involves redesign of storage elements which dynamically removes timing violation in critical paths. Also, new methods of approximate logic synthesis with smaller latency are investigated to replace the critical paths in ASIC designs.


Mahdieh Grailoo

PhD Candidate of Computer Engineering

Email: mgrailoo@ut.ac.ir

Many digital signal processing (DSP) systems require an efficient implementation of fixed-point data-paths on FPGAs or as ASICs. This is due to the trend for picking the cheapest hardware components that efficiently carry out the required computations without wasting too much energy. In the systems, the designer must balance the need for an efficient implementation with output quality under the effect of the well-known sources of arithmetic imprecision. They are including the finite word-length effect and quantization noise, where using a finite number of bits to represent real numbers results in precision loss. Many works have targeted the problem by using the design paradigm of accuracy-aware bit-width allocation to decrease the hardware cost of the implementations in an acceptable deviations from the nominal output values. Such studies mostly face with some weaknesses of wasting the error budget in the line with hardware saving, inaccurate error modeling, inability to handle recursive circuits, and overestimating range and error bounds. The thesis aims to address the weaknesses by enhancing the error modeling, accuracy in the range and error measures, as well as word-length optimization (WLO) for recursive and non-recursive systems through the analytical approaches.


Ali Azarmi

PhD Student

Email: aliazarmi@ut.ac.ir

In recent years, deep artificial neural networks (including recurrent ones) have won numerous contests in pattern recognition and machine learning. Learn about artificial neural networks and how they're being used for machine learning, as applied to speech and object recognition, image segmentation, modeling language and human motion, etc. The goal of my thesis is working with deep supervised learning, unsupervised learning, reinforcement learning and evolutionary computation to implement an useful and brain-based product in this area.


MSc Students


Shayan Moini

MSc Student

Email: moinishayan@gmail.com

Convolutional Neural Networks are known to be one of the most prominent and state of the art methods in visual and audio pattern recognition. The usage of CNNs in practical and industrial applications has increased drastically due to their impressing performance and accuracy and also the recent advances in high density computation platforms including Multi-core CPUs, GPUs, FPGAs, and so on. One of the major issues in utilizing these systems in real world applications is overcoming their enormous computational complexity in order to use them in time, memory, and power constrained systems. The main focus of my research is on overcoming these issues by using reconfigurable platforms – mainly FPGAs. I am developing a new architecture for accelerating Convolutional Neural Networks. The architecture is designated to exploit the inherent parallelism in CNNs in order to reduce their memory, resource, and power usage - especially computationally complex convolution layers - as required by real-time embedded applications. I am also working towards implementing the said architecture on a ZC706 evaluation board featuring a Xilinx Zynq-7000 System-on-Chip, where the hard ARM processor with high clocking speed is a great candidate to meet the flexibility and speed requirements of the present embedded systems.


Vahid saadatmand

MSc Student

Email: vahidsaadatmand2@gmail.com

The traditional and common encryption evaluation model only paid attention to analysis of applied functions in algorithm. This method analyzed the security of functions from the aspect of computation complexity according to the available processors power. Simple power analysis (SPA) and differential power analysis (DPA) can be noted as side channel attacks. In the SPA, the attacker directly uses the power consumption of commands and operators of an encryption system within the encryption, to break it. Another method is DPA. In this method, statistical features and error correction method are used to extract hidden information from the power consumption signal. In this study, we will introduce a hiding countermeasure method that leads to constant hamming weight and hamming distance for mean values and states, during the encryption operation.


Mahdi Shakeri

MSc Student

Email: en.mahdishakeri@gmail.com

The impact of timing variations on the performance of Very-Large-Scale Integrated (VLSI) circuits is increasing as the feature sizes shrink down into the nanometer scale. Timing variations induced by process, environmental or other effects may lead to a failing speedpath. Diagnosis of failing speedpaths is a major challenge in developing VLSI circuits. The goal of my thesis is to propose an efficient approach to automate speedpath debugging based on Quantified Boolean Formula (QBF).


Mojtaba Abbasnezhad

MSc Student

Email: mojtaba.abasnezhad@gmail.com

Distributed fiber optic sensing offers the ability to measure temperatures and strains at thousands of points along a single fiber. This is particularly interesting for the monitoring of large structures such as dams, dikes, levees, tunnels, pipelines and landslides, where it allows the detection and localization of movements and seepage zones with sensitivity and localization accuracy unattainable using conventional measurement techniques. The main challenges with Distributed fiber optic Sensors are the SNR of the backscatter signal and the Spatial Resolution of the system. The goal of my thesis is to improve these two parameters by signal processing techniques.


BSc Students


Sahand Salamat

BSc Student

Email: shndslmt@gmail.com

High level synthesis reduces the time of designing phase as well as the complexity of designs, multi dimensional nested loops are the "bottle neck" of behavioral code, As the high level descriptions with non-rectangular iteration spaces do not lend themselves well to efficient high level synthesis process, a reshaping technique is proposed to convert non-rectangular iteration spaces with certain inter-iteration dependencies to the rectangular ones. I am, also, doing some researches on approximate logic synthesis, which is a need due to the fact that quite a few applications are able to tolerate imprecise or approximated outputs in their underlying computations, in order to improve the energy efficiency of circuits. My future works are based on using the approximated circuits in different variety of applications, and also combine these circuits with state-of-the-art existing methods such as variable latency design in order to increase performance of VLSI circuits.


Former Students


MSc Students

Alireza Mahzoon

Arash Golgol

Bahman Ajami

Mehrzad Nejat

Hossein Mehri

Peyman Behnam

Farimah Farahmandi


BSc Students

Amir Samadi

Mohammadhosein Ghasemi

Ehsan Ghasemi

Seyed Sina Dezfouli

AmirHosein Borghei

Nazanin Farahpour

Sina Shahhoseini