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Publications

Journal Papers

  • SH. Moeini, B. Alizadeh, M. Emad, and R. Ebrahimpour, A Resource Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications, in IEEE Transactions on Circuits and Systems II (TCAS-II), 2017 (to appear).
  • M. Grailoo, B. Alizadeh, and B. Forouzandeh, Improved Range Analysis in Fixed-point Polynomial Datapath, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), 2017 (to appear).
  • F. Refan, B. Alizadeh, and Z. Navabi, Bridging Pre-silicon and Post-silicon Debugging of Instruction-based Trace Signal Selection in Modern Processors, in IEEE Transactions on VLSI (TVLSI), Vol. 25, No. 7, July 2017, pages 2059-2070.
  • A.R. Mahzoon, and B. Alizadeh, Systematic Design Space Exploration of Floating Point Expressions on FPGA, in IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 64, No. 3, March 2017, pages 274-278.
  • M.R. Azarbad, and B. Alizadeh, Scalable SMT-based Equivalence Checking of Nested Loop Pipelining in Behavioural Synthesis, in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 2, March 2017, Article No. 22.
  • H. Mehri, and B. Alizadeh, Analytical Performance Model for FPGA-based Reconfigurable Computing, in Journal of Iranian Association of Electrical and Electronics Engineers (JIAEEE), Vol. 13, No. 4, January 2017, pages 1-13.
  • M. Ahmadi, B. Alizadeh, and B. Forouzandeh, A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the presence of Variations, in IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 64, No. 1, January 2017, pages 100-110.
  • A.R. Mahzoon, and B. Alizadeh, OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs with Optimized Exponent/Mantissa Widths, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 1, January 2017, pages 198-209.
  • H. Mehri, and B. Alizadeh, Genetic Algorithm Based FPGA Architectural Exploration using Analytical Models, in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 1, December 2016, Article No. 13.
  • M. Grailoo, B. Alizadeh, and B. Forouzandeh, UAFEA: Unified Analytical Framework for IA/AA-based Error Analysis of Fixed-point Polynomial Specifications, in IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 63, No. 10, October 2016, pages 994-998.
  • H. Mehri, and B. Alizadeh, Analytical Performance Model for FPGA-based Reconfigurable Computing, in Microprocessors and Microsystems - Embedded Hardware Design , Vol. 39, No. 8, November 2015, pages 796-806.
  • M. Nejat, B. Alizadeh, and A. Afzali-kusha, Dynamic Flip-Flop Conversion: A Time Borrowing Method for Performance Improvement of Low Power Digital Circuits Prone to Variations, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 23, No. 11, October 2015, pages 2727-2724.
  • S. Ghandali, B. Alizadeh, M. Fujita, and Z. Navabi, Automatic High Level Data-flow Synthesis and Optimization of Polynomial Datapaths using Functional Decomposition, in IEEE Transactions on Computers (TC), Vol. 64, No. 6, June 2015, pages 1579-1593.
  • B. Alizadeh, P. Behnam, and S. Sadeghi-kohan, A Scalable Formal Debugging Approach with Auto-correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs, in IEEE Transactions on Computers (TC), Vol. 64, No. 6, June 2015, pages 1564-1578.
  • F. Farahmandi, and B. Alizadeh, Groebner Basis Based Formal Verification of Large Arithmetic Circuits using Gaussian Elimination and Cone-based Polynomial Extraction, in Microprocessors and Microsystems – Embedded Hardware Design, Vol. 39, No. 2, March 2015, pages 83-96.
  • B. Alizadeh, and P. Behnam, Formal Equivalence Verification and Debugging Techniques with Auto-correction Mechanism for RTL Designs, in Microprocessors and Microsystems – Embedded Hardware Design, Vol. 37, No. 8-D, November 2013, pages 1108-1121.
  • M. Mirzaei, M. Tabandeh, B. Alizadeh, and Z. Navabi, A New Approach for Automatic Test Generation in Register Transfer Level Circuits, in IEEE Design and Test of Computers, Vol. 30, No. 4, August 2013, pages 49-59.
  • B. Alizadeh, Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors, in ACM Transactions on Design Auotmation of Electronic Systems (TODAES), Vol. 17, No. 4, October 2012, pages 37-1:37-8.
  • B. Alizadeh, and M. Fujita, Modular Data-path Optimization and Verification Based on Modular-HED, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 9, September 2010, pages 1422-1435.
  • B. Alizadeh, M. Mirzaei and M. Fujita, Coverage Driven High Level Test Generation using a Polynomial Model of Sequential Circuits, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, May 2010, pages 737-748.
  • O. Sarbishei, M. Tabandeh, B. Alizadeh and M. Fujita, A Formal Approach for Debugging Arithmetic Circuits, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 5, May 2009, pages 742-754.
  • B. Alizadeh and M. Fujita, A Unified Framework for Equivalence Verification of Datapath-oriented Applications, in IEICE TRANS. INF. & SYST., Vol. E92-D, No. 5, May 2009, pages 985-994.
  • B. Alizadeh and Z. Navabi, Word Level Symbolic Simulation in Processor Verification, IEE Proceedings Computers and Digital Techniques Journal, Vol. 151, No. 5, September 2004, pages 356-366.
  • B. Alizadeh and Z. Navabi, A New High Level Model to Check CTL Properties in VHDL Environment, Iranian Journal of Electrical and Computer Engineering, Vol. 1, No. 2, April 2003, pages 92-98.