Bijan Alizadeh, Masahiro Fujita
2011 IEEE International Symposium of Circuits and Systems (ISCAS)
Publication year: 2011

Abstract

Early generation of effective high level test patterns can significantly reduce Automatic Test Pattern Generation (ATPG) efforts in gate level. This paper proposes an ATPG methodology targeting non-scan designs. Although our methodology checks all execution paths, a decision procedure is applied to detect the false paths very early and split the cases before generating high level test patterns. Experimental results show robustness and reliability of our method compared to FlexTest as a commercial gate level ATPG tool.