Publications

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LTED: a canonical and compact hybrid word-Boolean representation as a formal model for hardware/software co-designs

Conference
Bijan Alizadeh, Masahiro Fujita
4th International Workshop on Constraints in Formal Verification (CFV07)
Year of publication : 2007

High level test generation without ILP and SAT Solvers

Journal
B Alizadeh, M Fujita
International Workshop on High Level Design Validation and Testing (HLDVT07)
Year of publication : 2007

Cacoveanu, CR 82 Caldinhas Vaz, J. 204 Chaker, M. 249

Conference
IL Abdel-Hafez, B Afzal, A Afzali-Kusha, S Aghnout, N Akkouche, Z Al-Ars, S Albrecht, B Alizadeh, Z Amini-Sheshdeh, N Anane, M Anane, W Ang, C Anghel, H Antonopoulou, T Arslan, JG Atallah, F Azevedo, A Aziz, H Aziza, Y Bachelet, F Badets, S Bahramirad, M Baklouti, M Battista, N Benameur, D Benamrouche, M Benyahia, A Benzina, E Bergeret, H Bessalah, R Bhutada, F Boissieres, B Bornoosh, R Bouchakour, A Bouchhima, A Bounceur, OM Bugiugan, Y Chara, J Chen, K Cho, B Christianson, HY Darweesh, D Deschacht, G Ditlow, B Djezzar, C Egan, B Eghbalkhah, A El Oualkadi, A El Sanhoury, AA Enescu, S Eratne, AT Erdogan, A Fanei, FA Farag, T Finateu, D Flandre, F Fortes, OM Frioui, J Gaubert, B Ghavami, CE Goutis, SX Guo, F Haddad, M Hamdaoui, S Hamdioui, B Han, S Hanafi, L Hasan, F Hasani, E Hashish, F Heng
2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era
Year of publication : 2007

Automatic merge-point detection for sequential equivalence checking of system-level and RTL descriptions

Conference
Bijan Alizadeh, Masahiro Fujita
International Symposium on Automated Technology for Verification and Analysis
Year of publication : 2007

Automated Technology for Verification and Analysis: 5th International Symposium, ATVA 2007 Tokyo, Japan, October 22-25, 2007 Proceedings

Conference
Kedar Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura
2007 IEEE International High Level Design Validation and Test Workshop
Year of publication : 2007

A novel formal approach to generate high-level test vectors without ILP and SAT solvers

Conference
Bijan Alizadeh, Masahiro Fujita
2007 IEEE International High Level Design Validation and Test Workshop
Year of publication : 2007

A hybrid approach for equivalence checking between system level and RTL descriptions

Journal
Bijan Alizadeh, Masahiro Fujita
Proc. Int. Workshop Logic Synthesis (IWLS)
Year of publication : 2007

Word-level symbolic simulation in processor verification

Journal
B Alizadeh, Z Navabi
IEEE Proceedings-Computers and Digital Techniques
Year of publication : 2006

Word level functional coverage computation

Conference
Bijan Alizadeh
Asia and South Pacific Conference on Design Automation, 2006.
Year of publication : 2006

Using integer equations to check PSL properties in RT level design

Conference
Bijan Alizadeh, Zainalabedin Navabi
4th IEEE International Workshop on System-on-Chip for Real-Time Applications
Year of publication : 2006

Binary Taylor diagrams: An efficient implementation of Taylor expansion diagrams

Conference
Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, P Lotfi-Kamran, M Naderi, Z Navabi, B Alizadeh
2005 IEEE International Symposium on Circuits and Systems
Year of publication : 2006

Property checking based on hierarchical integer

Conference
Bijan Alizadeh, Zainalabedin Navabi
Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004.
Year of publication : 2004

Check high level properties in arithmetic circuits.

Journal
Bijan Alizadeh, HAMID SHOJAEE
WSEAS Transactions on Circuits and Systems
Year of publication : 2004

Using integer equations for high level formal verification property checking

Conference
Bijan Alizadeh, Mohammad Reza Kakoee
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.
Year of publication : 2003

A NEW HIGH LEVEL MODEL TO CHECK CTL PROPERTIES IN VHDL ENVIRONMENT

Journal
B ALIZADEH, Z NAVABI
NASHRIYYAH-I MUHANDESI-I BARQ VA MUHANDESI-I KAMPYUTAR-I IRAN (PERSIAN)
Year of publication : 2003

VLSID & ES 2018–List of Reviewers

Journal
Abhinav Kranti, Rajat Subhra Chakraborty, Gaurav Saini, Alex Doboli, Rajendra Patrikar, Govardhan Rao, Amey Kulkarni, Rajesh Bhagwat, Gregory Chang, Amir Masoud Gharehbaghi, Rajiv Joshi, Heba Khdr, Amit Patra, Ramesh Karri, Honglan Jiang, Amlan Ganguly, Rangharajan Venkatesan, Hwisoo So, Amol Dharangutte, Robert Karam, Jack Tang, Andreas Veneris, Robert Wille, Jiang Guiyuan, Ankur Gupta, Rolf Drechsler, Jing Ye, Ansuman Banerjee, Sachin Patkar, Ketan Budhiya, Arijit Mondal, Sandip Ray, Lokesh Siddhu, Arijit Raychowdhury, Santanu Mahapatra, Mahesh Balasubramanian, Aritra Hazra, Santosh Balasubramanian, Mahesh Kumashikar, Arnab Sarkar, Santosh Vishvakarma, Mandar Datar, Arun Joseph Seetharam Narasimhan Manikandan RR, Arya Rahimi, Sheikh Nijam Ali, Manish Rana, Aryabartta Sahu, Shigeru Yamashita, Marc Stöttinger, Aviral Shrivastava, Shivam Bhasin, Marcel Walter, Bai Nguyen, Shobha Vasudevan, Michael Shamouilian, Basant Dwivedi, Shreepad Karmalkar, Michele Lora, Bhargab Bhattacharya, Shreyas Sen, Mike Hayenga, Bibhu Datta Sahoo, Siddharth Garg, Mohammad Khayatian, Bijan Alizadeh, Siew Kei Lam, Mohammadreza Mehrabian, Bodhisatwa Mazumdar, Smruti R Sarangi, Morgan Ledwon, Brajesh Kumar Kaushik, Somyendu Raha, Moslem Didehban, Chandan Kumar Sarkar, Soumya Pandit, Piyoosh Purushottam Nair
2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
Year of publication : 1998

Component modeling for reliability analysis by simulation

Conference
Bijan Alizadeh, Zainalabedin Navabi
Proceedings VHDL International Users' Forum. Fall Conference
Year of publication : 1997

Integer Equation as a Model of VHDL-based Design to Check Safety and Liveness Properties without Equation Solving

Conference
Bijan Alizadeh, Mohammad R Kakoee, Hamid Shojaee, Zainalabedin Navabi
Year of publication : 1996

DW INTERNATIONAL TEST CONFERENCE

Conference
Magdy Abadir, Salem Abdennadher, Erkan Acar, Nisar Ahmed, Chidambaram Alagappan, Bijan Alizadeh, Juergen Alt
2013 IEEE International Test Conference (ITC)
Year of publication : 1996

CTL Property Checking Based on a New High Level Model Without Equation Solving

Conference
Bijan Alizadeh, Zainalabedin Navabi
Year of publication : 1996

Binary Taylor Diagrams (BTD): An Efficient Way of Implementing Taylor Expansion Diagrams

arXiv preprint
A Hooshmand, S Shamshiri, M Alisafaee, B Alizadeh, P Lotfikamran, M Naderi, Z Navabi
Year of publication : 1996

A New High Level Model Based on Integer Equations to Check CTL Properties in VHDL Environment

Conference
Bijan Alizadeh, Mohammad R Kakoee, Zainalabedin Navabi
Year of publication : 1996
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