Research Projects

  • A MAX-SAT-based hardware Trojan Detection using PMTP Approach

    By: Ahmad Shabani, Bijan Alizadeh

    This software has been created in Linux platform ubuntu 16.04 using Perl language. Executing PMTP_Method.out has some dependencies that are as follows:

    1- Install Modelsim simulator software for Linux and make sure that it can be executable from any path.

    2- Install open-wbo Max-SAT solver from below URL and make sure that it can be executable from any path
    https://github.com/sat-group/open-wbo

    3- Configure the config.txt file consisting of:

    * File name of Gate-level netlist benchmark (Design.v)
    * File name of test bench of netlist (TB_Design.v)
    * probability threshold (Pth)
    * Number of test vector required to simulate benchmark and extract probability statistic. This item will be set in testbench file
    * The time of clock cycle in ns. This item will be set in the testbench file.

    4- Run PMTP_Method.out by executing the following command:
    ./PMTP_Method

    5- By executing the above command, these outputs will be generated:

    * The Modified gate-level netlist (Design_sec.v) which contains the insertion points by applying PMTP rules and conflicts
    * Detailed information (InfoGate.txt) about the gate level netlist including:

    * Probability of every net (Probability)
    * Logic depth of every net (MaxDepth)
    * Gate Type (INPUT1, NOT1, AND2, NAND2, Or2, NOR2, …)
    * Fanins
    * Number of Transition for every net (TC)
    * The duration of being zero for every net (T0)
    * The duration of being one for every net (T1)
    * Transition Rate of every net (TR)

    * SAT solver result (SATSolver.txt)
    * Probability info for all the circuit nets (Probability.out)
    * fanout of all the circuit nets (fanout.out)
    * Modelsim script (script.do)
    * Map file of all the circuit nets (Design.map). Hint: all the circuit nets are mapped to the integer value before executing by SAT solver.
    * Value change dump (VCD) file of circuit netlist generated by Modelsim software to simulate dynamic transition probability calculation (Design.vcd)
    * Soft and hard clause of SAT instance (Design.wcnf)
    * All the soft clause of SAT instance which represent circuit logic in DMAIC format. for more info please visit (https://maxsat-evaluations.github.io/2018/)
    * backward SAIF file containing the transition info of all the circuit nets (Design_bw.saif)

     

    Download source files: PMTP-sources

    Please cite the following paper in case of any use:

    [1] Shabani, Ahmad, and Bijan Alizadeh. “PMTP: A MAX-SAT Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2018).

DVDES Lab

From simple home appliances to space shuttles, embedded systems are widely used. With the ever increasing complexity of embedded systems, design, verification and debug of such systems is becoming more and more challenging. Design of a complex embedded system requires engineering teams, precise plans and schedules, heavy computer simulations, and verification both before and after fabrication. At Design, Verification and Debugging of Embedded Systems (DVDES) Lab., we’re continuously looking for ways to facilitate the embedded system design flow through development of new tools and methods for fast realization of reliable high-performance embedded systems. With today’s complex systems, 70% of total design time consists of their verification and debug. DVDES Lab. aims to cut off this share by incorporating dynamic, assertion-based and formal verification steps in its tools and methods.

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Nafiseh Hosseinpour Fardi

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Mahdi Shokrollahi

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Abolfazl Sajadi

Abolfazl Sajadi

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Ahmad Shabani

Ahmad Shabani

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ahmadshabani89@gmail.com
Ali Azarmi Gilan

Ali Azarmi Gilan

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Fatemeh Khormizi

Fatemeh Khormizi

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Sahand Salamat

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Mehrnaz Ahmadi

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Shayan moini

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Mahdieh Grailoo

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MohamadReza Azarbad

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